在第一节我们提到,V2的开发板使用CP2102实现USB转串口的通信(乐鑫原厂开发板大多使用该芯片,其他品牌开发板有些使用CH340),这款芯片在windows10系统中可以自动安装驱动,保持电脑联网,插入设备即可,在Ubuntu16.04、18.04中实测也是可以直接使用的.如果遇到驱动问题,可以在SILABS官网下载.CP210x USB to UART Bridge VCP Drivers
username@dd111:~$ dmesg
[ 3106.111239] usb 1-10: new full-speed USB device number 5 using xhci_hcd
[ 3106.241340] usb 1-10: New USB device found, idVendor=10c4, idProduct=ea60
[ 3106.241350] usb 1-10: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[ 3106.241357] usb 1-10: Product: CP2102 USB to UART Bridge Controller
[ 3106.241363] usb 1-10: Manufacturer: Silicon Labs
[ 3106.241369] usb 1-10: SerialNumber: 0001
[ 3106.242743] cp210x 1-10:1.0: cp210x converter detected
[ 3106.242985] usb 1-10: cp210x converter now attached to ttyUSB0
1.2. 安装esptool.py
$ pip install esptool
官方esp-idf在进行make flash操作时,也是使用了这个工具
1.3. 查看esptool.py源代码
esptool.py:A serial utility to communicate & flash code to Espressif ESP8266 & ESP32 chips.
我们先进行一下芯片擦除操作,找一些线索
username@dd111:~$ sudo esptool.py --port /dev/ttyUSB0 erase_flash #可以不设置 --port, 默认为/dev/ttyUSB0
esptool.py v2.7 #esptool版本号
Serial port /dev/ttyUSB0 #操作的端口号
Connecting...... #尝试连接,与bootloader通信
Detecting chip type... ESP32 #检测到ESP32
Chip is ESP32D0WDQ5 (revision 0) #芯片型号
Features: WiFi, BT, Dual Core, Coding Scheme None #该型号配置
Crystal is 40MHz #晶振频率
MAC: 30:ae:a4:80:05:10 #硬件MAC地址
Uploading stub...
Running stub...
Stub running...
Erasing flash (this may take a while)...
Chip erase completed successfully in 1.1s
Hard resetting via RTS pin...
def _setDTR(self, state):
self._port.setDTR(state)
def _setRTS(self, state):
self._port.setRTS(state)
# Work-around for adapters on Windows using the usbser.sys driver:
# generate a dummy change to DTR so that the set-control-line-state
# request is sent with the updated RTS state and the same DTR state
self._port.setDTR(self._port.dtr)
# issue reset-to-bootloader:
# RTS = either CH_PD/EN or nRESET (both active low = chip in reset
# DTR = GPIO0 (active low = boot to flasher)
#
# DTR & RTS are active low signals,
# ie True = pin @ 0V, False = pin @ VCC.
if mode != 'no_reset':
self._setDTR(False) # IO0=HIGH
self._setRTS(True) # EN=LOW, chip in reset
time.sleep(0.1)
if esp32r0_delay:
# Some chips are more likely to trigger the esp32r0
# watchdog reset silicon bug if they're held with EN=LOW
# for a longer period
time.sleep(1.2)
self._setDTR(True) # IO0=LOW
self._setRTS(False) # EN=HIGH, chip out of reset
if esp32r0_delay:
# Sleep longer after reset.
# This workaround only works on revision 0 ESP32 chips,
# it exploits a silicon bug spurious watchdog reset.
time.sleep(0.4) # allow watchdog reset to occur
time.sleep(0.05)
self._setDTR(False) # IO0=HIGH, done
